--
-- VHDL Architecture Fietssimulator_lib.timer.v
--
-- Created:
--          by - John.UNKNOWN (EPOX)
--          at - 14:17:03 04/15/2009
--
-- using Mentor Graphics HDL Designer(TM) 2005.2 (Build 37)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY s_timer IS
  PORT( 
  time  : IN     STD_LOGIC_VECTOR(15 DOWNTO 0);
  start : BUFFER STD_LOGIC;
  ena   : IN     STD_LOGIC;
  clk   : IN     STD_LOGIC;
  rst   : IN     STD_LOGIC
  );
END ENTITY s_timer;

--
ARCHITECTURE v OF s_timer IS

SIGNAL q : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
  
  
  
  PROCESS(rst, clk)
    BEGIN
      IF rst = '1' THEN
        q <=  (OTHERS => '0');
      ELSIF RISING_EDGE(clk) THEN
        
        IF start = '1'  THEN
          q <= x"0002";
        ELSIF ena = '1' THEN
          q <= q + '1';
      END IF;    
        
      END IF;
    END PROCESS;
    
    
    start <= '1' WHEN q > time AND ena = '1' ELSE '0'; 
    
    
END ARCHITECTURE v;

